1. Field of the Invention
The present invention relates to an image rendering device and an image rendering method.
2. Description of the Related Art
Generally, even if, in a depth test and an alpha blend, a write process is performed in the same pixel position during the time from when a current value is read from a frame buffer until a value of a processing result is written, the result of the write process can not be reflected, and hence a correct processing result can not be obtained. Therefore, in a related art, there is a mechanism in which the position of a pixel being processed at present is held in a pixel processor and compared with the position of a pixel to be newly processed, and when the position of the pixel to be newly processed matches that of the pixel being processed, the completion of processing is waited for.
FIG. 1 is a block diagram showing the configuration of a related image rendering device. A rasterizer 10 shown in FIG. 1 performs the processing of expanding a polygon on an image memory on a pixel-by-pixel basis.
For example, pixel-by-pixel colors are determined by interpolating colors given to respective vertexes by a method called smooth shading. In this case, a pixel processor 20 hides (does not render) an object which is hidden behind another object and invisible by a hidden surface removal algorithm called a Z-buffer algorithm. This is also called a depth test. The pixel processor 20 includes a register 22 and an arithmetic unit 24, and frame buffer values in a memory 30 and values from the rasterizer are stored in sequence in the register 22, processed by texture mapping and a Z-buffer algorithm in the arithmetic unit 24, and stored again in the register 22. The contents of the register 22 are outputted to the memory 30 which is a frame buffer. Accordingly, when the memory 30 acquires an operation result from the register 22, it is required to determine by comparison whether a processing position which is being processed by the arithmetic unit 24 and a processing position which is to be acquired from the memory 30 match each other, and when these processing positions match each other, to wait for the start of the processing of the corresponding pixel.
However, with an increase in the clock frequency of LSI, latency in processing (time from when data is inputted to the register 22 in FIG. 2 until the data is outputted) becomes longer, whereby the number of pixels which need to be held increases, which causes problems of enlargement of a comparator and an increase in stop rate due to a match between processing positions.
On the other hand, due to an increase in the scale of the LSI, the degree of parallelism for pixel processors which can be mounted on the LSI increases, but in the related art, only part of many arranged pixel processors can be brought into operation in small polygon processing, and hence the processing efficiency does not increase as much as the circuit scale.